IA-64 Performance-oriented programming
IA-64
has a rich instruction set with a great potential for good performance. I have
identified a set of what I call "Key Performance Enablers"
that could make the difference between 
and
as
far as performance is concerned. The list is as follows:
- Use
of Predication (for if-conversion of small blocks)
- Software
Pipelining (of all important loops)
- SIMD
Vectorisation (i.e. use of integer or floating-point SIMD instructions)
- Wide
Execution (Itanium dispatches two bundles n parallel, each with 3
instructions)
- Use
of Memory Control instructions (Prefetching and Branch Predict)
One
natural domain for using these Key Performance Enablers is, for instance, a
mathematical kernel. I have chosen Random Number Generators (RNGs). These can
be programmed very effectively on IA-64 by generating arrays of random numbers
in one go. As a proof of concept, at CERN I have coded up both RANMAR48 and the
Mersenne Twister in IA-64 assembly, so that each needs only 4 cycles for
producing a Random Number and storing it in an output array. Doing the same without enabling Key Performance Enablers,
such as Predication, Software Pipelining and Wide Execution, can easily take
10-20 times longer.
The
whole
concept was presented, for instance, at the Itanium Developers’ Conference in
Amsterdam in Nov. 2000.
There
are many other programming domains that seem to offer similar performance
advantages, such as:
- Histogramming
and Pattern Recognition Software
- Matrix
and Vector calculations (integer or floating-point)
- Transcendental
Math Functions
- IP
Checksumming
- Memory/String
Manipulation Routines
- Cryptography
(The new Rijndael algorithm selected by AES is a very good example)
- Multimedia
Software
Last updated: 25 June
2001 - Sverre Jarp